Field of the Invention
The present invention relates to a semiconductor device, for example, a semiconductor device including a semiconductor memory, and a circuit for and method of searching for a data erasure count in the semiconductor memory.
Description of the Related Art
A flash memory has been known as a non-volatile semiconductor memory in which data can be rewritten and no data is erased even when power is turned off. Especially in a NAND type flash memory, upon writing data, data erasure is first performed in a block unit composed of a plurality of memory cells. Due to an upper limit in the erasable number of times in each of the blocks, however, it is necessary to manage the erasure count for the blocks in the memory as needed. In view of this, a semiconductor storage equipped with: a RAM (Random Access Memory) that stores, corresponding to each of blocks in a flash memory, erasure count data representing an erasure count performed in the block; and a CPU that performs control of reading the erasure count data from the RAM and searching for a block with a minimum erasure count has been proposed (see Japanese Patent Application Laid-Open No. 2008-123314, for example). Such a CPU repeatedly provides a read instruction to the RAM to read the erasure count data for the blocks one by one and compares in size the erasure count data for the blocks. In this manner, the CPU searches for the block with the smallest erasure count as an erasure target. Therefore, the CPU repeatedly executes a series of control, composed of read control for reading the erasure count data corresponding to one block and comparison control for comparing the erasure count data, for the number of times equal to the number of all the erasure count data stored in the RAM. In order to sequentially execute these read control and comparison control by the CPU, however, a large amount of time is consumed for the search due to interventions of instruction fetch cycles for specifying such control.